Marvell Unveils AI Memory Bottleneck Solutions with 260-Lane CXL Switch
Prefer us on GoogleMarvell Technology announces its strategy to alleviate memory and storage bottlenecks in AI infrastructure through its 260-lane CXL switch. The increasing context processing demands of large language models (LLMs) are spreading the burden on data centers across memory capacity and bandwidth. Marvell will present on AI infrastructure at the Future of Memory and Storage 2026 event, taking place from March 5 to 7 in Santa Clara, California. Topics of the presentations will include 'Data Storage Innovations for Scalable AI Infrastructure' and 'The Memory-Centric Era: The Future of CXL and Scalable AI Infrastructure.' Marvell introduced its next-generation CXL switch, the 'Structera S 30260,' on March 17, which supports up to 48 terabytes of shared memory and provides up to 4 terabytes of aggregated bandwidth via CXL 3.0. According to Marvell's testing results, when a 16-terabyte memory pool was shared among 8 GPUs and 2 CPU servers, inference throughput improved by 4.8 times, and the time to generate the first token was reduced by 82.7%. Marvell and NVIDIA are expanding their collaboration on AI infrastructure and announced on March 31 that they will work together based on NVLink Fusion. Customer sampling for the Structera S 30260 is expected to begin in the third quarter of 2026.
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